How can I escape 0.5mm ball grid array pins if the trace spacing and via hole size is not allowed to reduce?

I have a small hobby project in which I want to include the Kingston EMMC04G-M657 eMMC chip. This chip comes in BGA packaging with 0.5mm pitch between balls. I want my board to be cheap, so I'm laying it out for a 4-layer PCB using rigid board design rules of my supplier. I've put these rules into KiCAD and it seems to me that there are a few pins that I can neither escape from the BGA with a trace nor disappear with a via. How can I move on?

For this sort of routing, you will need to do a ‘via-in-pad’ technology. Essentially, just place the via centered on the pad.

Ask your supplier to offer this on their 6-layer process standard and on a 4-layer board for an extra charge. This is called ‘plating overfilled via’.

Read More: Multilayer PCB

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Oliver Smith

Oliver is an experienced electronics engineer skilled in PCB design, analog circuits, embedded systems, and prototyping. His deep knowledge spans schematic capture, firmware coding, simulation, layout, testing, and troubleshooting. Oliver excels at taking projects from concept to mass production using his electrical design talents and mechanical aptitude.
Picture of Oliver Smith

Oliver Smith

Oliver is an experienced electronics engineer skilled in PCB design, analog circuits, embedded systems, and prototyping. His deep knowledge spans schematic capture, firmware coding, simulation, layout, testing, and troubleshooting. Oliver excels at taking projects from concept to mass production using his electrical design talents and mechanical aptitude.

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